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Verilog Code for 1 to 4 DEMUX | 1 to 4 DEMUX Verilog Code

This page of Verilog source code section covers 1 to 4 DEMUX Verilog code. The block diagram and truth table of 1 to 4 DEMUX Verilog code is also mentioned.

Block Diagram of 1 to 4 DEMUX

1 to 4 DEMUX Block Diagram

Truth Table of 1 to 4 DEMUX

1 to 4 DEMUX Truth Table

1 to 4 DEMUX Verilog code

module demux1_4(a_in, sel, y_out);
input a_in;
input [1:0] sel;
output [3:0] y_out;
reg [3:0] y_out;
always @(a_in, sel)
case (sel)
2'b00:begin y_out[0]=a_in; y_out[1]= 1'b0;
y_out[2]= 1'b0;y_out[3]=1'b0; end
2'b01: begin y_out[0]= 1'b0;y_out[1]=a_in;
y_out[2]= 1'b0;y_out[3]=1'b0; end
2'b10: begin y_out[0]= 1'b0;y_out[1]=1'b0;
y_out[2]=a_in; y_out[3]=1'b0; end
2'b11: begin y_out[0]= 1'b0; y_out[1]= 1'b0;
y_out[2]=1'b0;y_out[3]=a_in; end
default: y_out=3'b000;


Refer following as well as links mentioned on left side panel for useful VHDL codes.
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USEFUL LINKS to Verilog Codes

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