The intel 8051 microcontroller supports about 5 interrupt sources which includes two external interrupts, two for timer interrupts, and one as serial port interrupt.
The External Interrupts INT0 and INT1 can each be either level triggered or edge triggered. This depends on bits IT0 and IT1 provided in the Register TCON. The flags which generate these type of interrupts are bits IE0 and IE1.
When an external interrupt is generated, the flag that generated the interrupt is cleared by the hardware when the service routine is vectored to ISR location. This happens only if the interrupt was edge-triggered. If the interrupt was level-triggered, then the external requesting source is what controls the requested flag, rather than the on-chip hardware.
Timer-0 & Timer-1 Interrupts are generated by registers TF0 and TF1.
When the timer interrupt is generated, the flag that generated the insterrupt is cleared by the on-chip hardware when the program is entered in the interrupt service routine.
The Serial Port Interrupt is generated by the logical-OR of registers RI/TI. These flags are not cleared by hardware,when the service routine is vectored. It is the service routine which need to determine whether it was RI or TI that generated the interrupt.
IE and IP are the registers to enable and to set priority of the interrupt system in the microcontroller.
IP(Interrupt Priority register), Bit addressable
• PS- IP.4- Serial Port Interrupt Priority bit
• PT1- IP.3- Timer 1 Interrupt Priority bit
• PX1- IP.2 External Interrupt 1 Priority bit
• PT0- IP.1 Timer 0 Interrupt Priority bit
• PX0- IP.0 External Interrupt 0 Priority bit
IE(Interrupt Enable register), Bit addressable
• ES-IE.4 Serial Port Interrupt Enable bit
• ET1-IE.3 Timer 1 Overflow Interrupt Enable bit
• EX1-IE.2 External Interrupt 1 Enable bit
• ET0-IE.1 Timer 0 Overflow Interrupt Enable bit
• EX0-IE.0 External Interrupt 0 Enable bit