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ARM register set,processor models and pipeline concept

This ARM tutorial covers ARM register set, processor models and pipeline concept. Refer following pages for other ARM tutorial contents.

Num of Registers : Total 37 registers. 20 (banked) not visible at all times. Min 17 visible in all modes. 16 general purpose, 1 status related.

Banked Registers: Each mode has a set of extra registers called banked registers. Banked registers are swapped in whenever mode change happens.

R13 - SP; holds stack head in the current processor mode.

R14 - LR( points to the return address when calling subroutine)

R15 - PC. Program counter. Contains the address of the next instruction to be fetched by the processor.

ARM Register

User System FIQ IRQ SVC Undef Abort
ro ro ro ro ro ro
r1 r1 r1 r1 r1 r1
r2 r2 r2 r2 r2 r2
r3 r3 r3 r3 r3 r3
r4 r4 r4 r4 r4 r4
r5 r5 r5 r5 r5 r5
r6 r6 r6 r6 r6 r6
r7 r7 r7 r7 r7 r7
r8 r8_fiq r8 r8 r8 r8
r9 r9_fiq r9 r9 r9 r9
r10 r10_fiq r10 r10 r10 r10
r11 r11_fiq r11 r11 r11 r11
r12 r12_fiq r12 r12 r12 r12
r13/SP r13_fiq r13_irq r13_svc r13_undef r13_abort
r14/LR r14_fiq r14_irq r14_svc r14_undef r14_abort
r15/PC r15/PC r15/PC r15/PC r15/PC r15/PC
SPSR - - - - -
- SPSR_fiq SPSR_irq SPSR_SVC SPSR_undef SPSR_abort

ARM Processor Modes:

Abort, FIQ, IRQ, Supervisor, System, User, undefined are the processor modes.
Abort: when memory read/write fails.
FIQ, IRQ : related to the interrupts in ARM.
Supervisor : After reset and is usually the mode the kernel operates.
System Mode: Special version of user mode and allows a full access to the CPSR.
Undefined mode : entered when encountering an undefined instruction.

Modes can be either privileged(all minus user mode)/un-privileged(user).
Determines which of the registers are active and who has access rights to the CPSR.
A privileged mode allows full read-write access to the CPSR.
Unprivilaged mode only allows a read access to CPSR mode field, but read/write access to the condition flags.

Table-2, ARM conditional flags

Flag Flag name Set When
Q Saturation the result causes an overflow and/or saturation
V Overflow the result causes a signed overflow
C Carry the result causes an unsigned carry
Z Zero the result is zero, frequently used to indicate equality
N Negative Bit 31 of the result is a binary 1

ARM Pipeline Characteristics

pipeline characteristics

As we know that more the stages means higher frequency, higher system latency.

Pipeline & PC Relation:
In ARM state,
PC = Current instruction add + 8.
In Thumb mode,
PC = current instruction +4

Other Characteristics: In legacy ARM core, Executing branch causes pipeline flush. Branch prediction is used to reduce effects of pipeline flush.

An interrupt will not be serviced till the instruction in the execute stage is serviced. Instructions in the pipeline is flushed on a interrupt.

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