8085 Architecture | 8085 microprocessor architecture
The intel 8085 is 8 bit size microprocessor produced by Intel in the year 1976. The major features of 8085 chip are 8 bit data bus, 16 bit address bus, 3.072 MHz internal clock frequency, 40 pin configuration etc. It uses +5V supply voltage for its operation. Let us understand 8085 microprocessor architecture with its internal modules or units.
The 8085 architecture consists of control unit, ALU, registers, accumulator, flags, program counter, stack pointer, Instruction register, memory address register, control register etc.
The 8085 chip is 8-bit general purpose microprocessor which can address 64K Byte size of memory.
Figure:1 8085 Microprocessor Architecture block diagram
Figure-1 depicts internal architecture of 8085 microprocessor.
Broadly 8085 architecture consists of three units viz.
processing unit, instruction unit, storage and interface unit.
➨Processing Unit consists of ALU, Accumulator, Status FLags and Temporary Register.
➨Instruction Unit consists of Instruction register, Instruction Decoder, Timing and Control Unit.
➨Storage and Interface Unit consists of general purpose regsiters, stack pointer(SP), program counter(PC), Increment/Decrement Register, Address Latch, Address/Data Latch.
➨The other three units are Interrupt Controller, Serial I/O Controller and Power Supply unit as shown in the figure.
All these hardware modules as part of 8085 architecture have been shown in the figure with its respective pins used in 8085 chip. Refer functions of all the 8085 pins below in the table.
8085 Pin Diagram
Figure:2 8085 Pin Diagram
Figure-2 depicts 8085 pin diagram.
8085 microprocessor has 40 pins. It uses +5V supply and runs on maximum frequency of about 3 MHz.
The pins on 8085 chip can be grouped into 6 groups:
• Address Bus
• Data Bus
• Control and Status Signals
• Power supply and frequency
• Externally Initiated Signals
• Serial I/O ports
|AD0 to AD7||There are bi-directional. They serve as address and data bus. During the instruction execution, these lines act as address bus initially and later serve as data bus lines. Externally Latch is interfaced with these lines.|
|A8 to A15||These are address bus lines which are uni-directional.|
|ALE||(Address Latch Enable), it is a pulse which holds value 1 when AD-AD7 lines are used as address bus. It takes value 0 after this. This is used to enable latch connected externally.|
|RD'||Read signal which is active low.|
|WR'||Write signal which is active low.|
|IO/M'||This signal specifies whether the operation is a memory operation(IO/M' = 0) or a I/O operation (IO/M' = 1).|
|S1, S0||These are status signals which specify kind of operation being performed by
|SID||Serial Input Data line. The data on this line is loaded into accumulator bit-7 whenever a RIM instruction is executed.|
|SOD||Serial Output Data line. The output SOD is set or reset as specified by SIM instruction.|
|INTR||Input,Interrupt Request. It is used as a general purpose interrupt. INTR is enabled and disabled by the software. It is disabled by reset and immediately after an interrupt is accepted.|
|INTA'||Output, Interrupt acknowledge; It is used instead of RD during instruction cycle after an INTR is accepted. It can be used to activate 8259 interrupt chip or some other interrupt port.|
|RST5.5,RST6.5,RST7.5||These are three inputs which has same timing as INTR except they cause internal RESTART to be automatically inserted. RST 7.5 has highest priority, RST 5.5 has lowest priority. These interrupts have higher priority than INTR.|
|TRAP||Input, TRAP interrupt is a nonmaskable restart interrupt. It is unaffected by any mask or interrupt enable. It has highest priority of any interrupt.|
|RESET IN (Input)||Reset sets the Program Counter (PC) to zero. It resets interrupt enable and HLDA flipflops. None of the other flags or registers are affected. CPU is held in reset condition as long as RESET is applied.|
|RESET OUT (Output)||Indicates CPU is being reset. It can be used as system RESET. The signal is synchronized to the processor clock.|
|CLK OUT||An output clock pin to drive the clock of the rest of the system.|
|READY (Input)||If this signal is high during a read or write cycle, it indicates that memory or peripheral is ready to send or receive data. If READY is low, CPU will wait for READY to go HIGH before completing the read or write cycle.|
|HOLD (input)||HOLD indicates that another MASTER is requesting the use of Address and Data Buses. The microprocessor (CPU) upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is removed.|
|HLDA (Output)|| HOLD ACKNOWLEDGE
It indicates that the CPU has received the Hold request and will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.
|X1,X2||These signals are inputs from crystal or clock generator.|
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