MIPI C-PHY vs MIPI D-PHY-Difference between MIPI C-PHY,D-PHY
This page compares MIPI C-PHY vs MIPI D-PHY mentions basic difference between MIPI C-PHY and MIPI D-PHY.
MIPI stands for Mobile Industry Processor Interface. It defines set of physical layers such as M-PHY, C-PHY and D-PHY for camera, display and chip to chip communication.
MIPI defines protocol interface specifications for the following.
• application processor and camera
• application processor and display
• Baseband and RF IC
Following are the features of MIPI variants C-PHY V1.0 and D-PHY V1.2.
• Both are efficient uni-directional streaming interface.
• Support low speed in-band reverse channel.
| Specifications | MIPI C-PHY | MIPI D-PHY |
|---|---|---|
| Full form | C stands for CSI (Camera Serial Interface) | D stands for DSI (Display Serial Interface) |
| Function | specifies serial interface between processor and camera module. | specifies serial interface between processor and display module. |
| Clock mechanism | Uses embedded clock | Uses DDR source sync clock |
| channel equalization | encoding to reduce data toggle rate | data skew control relative to clock |
| configurations | 1 lane (trio), simplex, 3 pins | 1 lane plus clock , simplex, 4 pins |
| max. transmitter swing amplitude | LP: 1300 mV (peak), HS: 425 mV (peak) | LP: 1300 mV (peak), HS: 360mV (peak) |
| HS (data rate per lane) | 80Msym/sec to 2.5 Gsym/sec times 2.28 bit/sym OR 5.7 Gbps (MAX) Aggregate |
80 Mbps to approx. 2.5 Gbps (Aggregate) |
| LS (Data rate per lane) | < 10 Mbps | < 10 Mbps |
| BW per port (3 or 4 lanes) | Approx. 17.1 Gbps per 3 lane port (Aggregate) (Maximum) | Approx. 10 Gbps per 4 lane port (Aggregate) (Maximum) |
| Typical pins per port (3 or 4 lanes) | 9 (3 lanes) | 10 (4 lanes, 1 lane clock) |
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