Advantages of JESD204B | Benefits of JESD204C interface
This page covers benefits or advantages of JESD204 interfaces viz. JESD204B and JESD204C. It mentions advantages of JESD204B interface and benefits of JESD204C interface.
What is JESD204 interface ?
In recent years, ADCs (Analog to Digital Converters) and DACs (Digital to Analog Converters) have gone through major improvement in terms of speed and resolution. It is challenging to connect these ADCs/DACs with FPGA/ASIC. JESD204 specifications have been developed to meet this interface requirement between converters and FPGA/ASIC. It is better to its predecessors CMOS and LVDS in terms of speed, size and cost. The interface has reduced pin count which helps to build smaller board designs. The JESD204 standard is scalable which meets changing needs of the future. JESD204 standard defines multi-gigabit serial data link between converters and receiver device such as FPGA/ASIC.
Following are the series of JESD204 standards.
JESD204A : Published in 2008; Lane Rate (Maximum) : 3.125 Gbps; Encoding : 8B/10B
JESD204B : Published in 2011; Lane Rate (Maximum) : 12.5 Gbps; Encoding : 8B/10B
JESD204C : Published in 2017; Lane Rate (Maximum) : 32.5 Gbps; Encoding : 8B/10B, 64B/66B, 64B/80B
Benefits or advantages of JESD204 interface
Following are the generic benefits or advantages of JESD204 interface. The same benefits are applicable to JESD204A, JESD204B and JESD204C.
➨Reduced/simplified PCB area
➨Reduced package size
➨Comparable power for large throughput
➨Scalable to higher frequencies
➨Simplified interface timing
What is JESD204C interface ?
Following are the features of JESD204C interface type.
• Backward compatible with JESD204A and JESD204B standard versions.
• It supports interface requirements of high megabit and gigabit data rates for various applications such as 5G cellular equipments, test equipments, medical devices, military warfare and so on.
• It supports all the features of JESD204B and added new benefits.
• Supports single or multiple lanes, serial lane alignment and monitoring, lane synchronization
• Modular design which supports multi-device synchronization
• It supports device subclasses viz. subclass-0 and subclass-1. Subclass-0 supports no deterministic latency. Subclass-1 uses SYSREF signal to support deterministic latency.
• LEMC (Local Extended Multiblock Counter) for deterministic latency and multichip synchronization
• Encoding : 8B/10B, 64B/66B, 64B/80B
• Scrambling and descrambling with polynomial : 1 + X39 + X58
• No FEC support
• MAC and PHY partitioning
Benefits or advantages of JESD204C over JESD204B
Following are the benefits or advantages of JESD204C interface over JESD204B:
➨It offers better DC balance, clock recovery and data alignment compare to JESD204B.
➨The bit overhead is 3.125% which is much smaller than JESD204B (~ 25%).
➨It supports CRC-12 which helps in error detection of the frames.
➨It supports about 256 maximum frames in a multi-frame compare to JESD204B (~32).
➨Refer standard specifications published on jedec.org for complete information on JESD204 interface and its versions.