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VHDL code to generate Ramp Wave using DAC

This page of VHDL source code section covers VHDL code to generate Ramp Wave using DAC.

VHDL code to generate Ramp Wave using DAC

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sawwave is
port(clk,rst:in std_logic;
dac_out:out std_logic_vector(7 downto 0));
end sawwave;
architecture Behavioral of sawwave is
signal counter : std_logic_vector(7 downto 0);
signal div: std_logic_vector(3 downto 0);
signal clkdiv:std_logic;
begin
process(clk)
begin
if (rising_edge(clk)) then
div <= div + '1' ;
end if;
end process;
clkdiv<=div(3);
process(clkdiv)
begin
if rst='1' then
counter <= "00000000";
elsif (rising_edge(clkdiv)) then
counter <= counter + 1 ;
end if;
end process;
dac_out<=counter;
end Behavioral;


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