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DC motor to FPGA interface VHDL source code

This page of VHDL source code covers DC motor to FPGA interface vhdl code.

VHDL Code

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;

Entity dcmotor1 is
Port (start,dir,clk:in std_logic;
pwm_out:out std_logic;
out_dc:out std_logic_vector(1 downto 0));
end dcmotor1;

architecture dcmotor_a1 of dcmotor1 is
signal clk1:std_logic;
signal div:std_logic_vector (24 downto 0);
begin
process (clk,start)

begin
if(start='0') then
div<="0000000000000000000000000";
elsif(clk' event and clk='1')then
div<=div+1;
end if;
clk1<=div(19);
end process;
process(clk1)
begin
if(clk1'event and clk='1')then
if start='0' then
out_dc<="00";
elsif start='1' and dir='1' then
out_dc<="10";
pwm_out<="1";
elsif start='1' and dir='0' then
out_dc<="01";
pwm_out<='1';
end if;
end if;
end process;
end dcmotor_a1;

FPGA XC2S100TQ144-5

Connector Device Pin Property
18 Clk
P18/6 44 Dir
P18/13 54 Out_dc(0)
P18/14 56 Out_dc(1)
P18/11 50 Pwm_out
P18/5 43 Start

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