Home of RF and Wireless Vendors and Resources

One Stop For Your RF and Wireless Need

D Latch VHDL source code

This page of VHDL source code covers D Latch vhdl code.

VHDL Code


entity mydlatch1 is port (
signal d, g: in std_logic;
signal q: out std_logic
);
end mydlatch1;

architecture behavior of mydlatch1 is
-- rising edge triggered DFF
state: process (g, d)
if (g = '1') then
q < = d;
end if;
end process;
end behavior;

USEFUL LINKS to VHDL CODES

Refer following as well as links mentioned on left side panel for useful VHDL codes.
D Flipflop
T Flipflop
Read Write RAM
4X1 MUX
4 bit binary counter
Radix4 Butterfly
16QAM Modulation
2bit Parallel to serial

RF and Wireless tutorials

WLAN  802.11ac  802.11ad  wimax  Zigbee  z-wave  GSM  LTE  UMTS  Bluetooth  UWB  IoT  satellite  Antenna  RADAR 


Share this page

Translate this page