4 Bit BCD Synchronous Reset Counter VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bcd_syn is
port (clk, rst: in std_logic;
bcd_out: out std_logic_vector(3 downto o));
end bin_syn;
architecture behavioral of bin_syn is
signal div:std_logic_vector(22 downto 0);
signal clkdiv:std_logic;
begin
process (clk)
begin
if rising_edge(clk) then
div<=div+1;
endif;
end process;
clkdiv<=div(22);
process (clkdiv)
variable temp:std_logic_vector(3 downto 0);
begin
if (rising_edge(clkdiv))then
if (rst='0' or temp= "1001") then
temp:="0000";
else
temp:=temp+'1';
end if;
end if;
end process;
bcd_out<=temp;
end ;