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VHDL Code for 2 to 4 decoder | 2 to 4 Decoder VHDL Code

This page of VHDL source code section covers 2 to 4 Decoder VHDL Code. The block diagram and truth table of 2 to 4 Decoder VHDL Code is also mentioned.

Block Diagram of 2 to 4 Decoder


2 to 4 Decoder Block Diagram

Truth Table of 2 to 4 Decoder


2 to 4 Decoder Truth Table

2 to 4 Decoder VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder2_4 is
port (en: in std_logic;
d_in: in std_logic_vector (1 downto 0);
d_op: out std_logic_vector (3 downto 0));
end decoder2_4;
architecture behavioral of decoder2_4 is
begin
process (en, din)
begin
if (en ='1') then
d_op <= "ZZZZ";
else
case (d_in) is
when "00" => d_op <= "0001";
when "01" => d_op <= "0010";
when "10" => d_op <= "0100";
when "11" => d_op <= "1000";
when others => null;
end case;
end if;
end process;
end ;


USEFUL LINKS to VHDL CODES

Refer following as well as links mentioned on left side panel for useful VHDL codes.
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USEFUL LINKS to Verilog Codes

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