16QAM Modulation VHDL Source Code
VHDL source code for 16QAM modulation implementation. Includes entity and architecture declarations for QAM modulation.
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1x8 Demultiplexer VHDL Source Code
VHDL source code for a 1x8 demultiplexer (DEMUX) implementation. Includes code and related VHDL resources.
2-Bit Parallel to Serial Conversion VHDL Code
VHDL code for a 2-bit parallel to serial converter implementation. Includes code, architecture, and port descriptions.
2-bit Serial to Parallel Conversion in VHDL
VHDL code for a 2-bit serial-in parallel-out (SIPO) converter, including code explanation and links to related VHDL resources.
3-to-8 Decoder VHDL Source Code
VHDL source code for a 3-to-8 decoder implementation, demonstrating a basic digital logic circuit.
4 Bit BCD Asynchronous Reset Counter VHDL Code
VHDL source code for a 4-bit BCD asynchronous reset counter is presented, detailing its architecture and functionality.
4-Bit BCD Synchronous Reset Counter VHDL Code
VHDL code for a 4-bit BCD synchronous reset counter, including a block diagram, truth table, and code explanation.
4-Bit Binary Asynchronous Reset Counter VHDL Code
VHDL source code for a 4-bit binary asynchronous reset counter, along with its block diagram and truth table.
4-Bit Binary Synchronous Reset Counter VHDL Code
VHDL source code for a 4-bit binary synchronous reset counter, along with a block diagram and truth table.
4-Bit Braun Multiplier VHDL Code
VHDL source code implementation of a 4-bit Braun multiplier, commonly used in digital signal processing and computer arithmetic.
4-Bit Up/Down Counter VHDL Source Code
VHDL source code for a 4-bit up/down counter with reset, load, and direction control.
4X1 Multiplexer (MUX) VHDL Source Code
VHDL source code implementation of a 4X1 Multiplexer (MUX).
64QAM Modulation VHDL Source Code
VHDL source code for 64QAM modulation, including entity declaration and architecture for data mapping.
7-Segment Display Interface VHDL Source Code
VHDL code for interfacing with a 7-segment display, including entity declaration and architecture implementation.
8 to 3 Encoder Without Priority: VHDL Code Implementation
VHDL source code for an 8 to 3 encoder without priority. Includes block diagram, truth table, and VHDL code implementation.
8-to-3 Encoder VHDL Source Code
VHDL source code for an 8-to-3 encoder implementation, demonstrating a simple combinational logic circuit.
8-to-3 Priority Encoder VHDL Code
VHDL implementation of an 8-to-3 priority encoder, including the block diagram, truth table, and the complete VHDL code.
ADC DAC Interfacing with FPGA using VHDL
Explore ADC DAC interfacing with FPGA, including VHDL code examples for reading data from ADC to receive and writing data to DAC for transmit.
Any Sequence Counter VHDL Code
VHDL source code for an 'Any Sequence Counter', including code snippet and useful links to VHDL and Verilog resources.
Barrel Shifter VHDL Code and Test Bench
VHDL code for a Barrel Shifter is presented, along with a test bench and simulation/synthesis results using ModelSIM and Leonardo Spectrum.
BCD Up/Down Counter VHDL Source Code
VHDL code examples for BCD up and down counters, including complete, synthesizable code blocks.
Binary to Gray Code Conversion in VHDL
VHDL code for converting binary numbers to Gray code using XOR operations. Efficient implementation for digital design.
BPSK Modulation VHDL Source Code
VHDL source code for BPSK modulation, including links to BPSK modulation basics for fundamental understanding.
Carry Select Adder and Carry Skip Adder: VHDL Code and Explanation
Explore Carry Select and Carry Skip adders with VHDL code. Learn their implementations and advantages in digital circuit design.
Convolutional Encoder VHDL Source Code
VHDL source code for a convolutional encoder with FEC rate 1/2, constraint length 7, and generator polynomials G1=171 (octal) and G2=133 (octal).
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