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Half Adder HDL Verilog Code

This page of verilog sourcecode covers HDL code for half adder, half substractor, full substractor using verilog.

The half adder truth table and schematic (fig-1) is mentioned below. The boolean expressions are:

S= A (EXOR) B
C=A.B

Input-A Input-B Output-S Output-C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Half Adder Schematic

half adder schematic

Half Adder Verilog code

module ha ( a, b, s, c)
input a, b;
output s, c;
assign s= a ^ b;
assign c= a & b;
end module

Half Substractor

The half substractor truth table and schematic (fig-2) is mentioned below. The boolean expressions are:

D= A (EXOR) B
Br=A'.B

Input-A Input-B Output-D Output-Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Half substractor Schematic

half substractor schematic

Half Substractor Verilog code

module hs ( a, b, d, br)
input a, b;
output d, br;
assign d= a ^ b;
assign br= ~a & b;
end module

Full Substractor

The full substractor truth table and schematic (fig-3) is mentioned below. The boolean expressions are:

D= A (EXOR) B (EXOR) C
Br=A'.B + B.Cin + A'.Cin

Input-A Input-B Input-Cin Output-D Output-Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Full substractor Schematic

full substractor schematic

Full Substractor Verilog code

module fs ( a, b, c, d, br)
input a, b, c;
output d, br;
assign d= a ^ b ^ c;
assign br=(( ~a)& (b ^ c)) | (b & c);
end module

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