Home of RF and Wireless Vendors and Resources

One Stop For Your RF and Wireless Need

Binary Up Down Counter HDL Verilog Code

This page of verilog sourcecode covers HDL code for binary up down counter using verilog.

Symbol

Following is the truth table of binary up/down counter.

binary up down counter

Truth Table

Clk Rst Qout
X 1 0000
1 0 0001
1 0 0010
1 0 0011
1 0 0100
1 0 0101
1 0 0110
1 0 0111
1 0 1000
1 0 1001
1 0 1010
1 0 1011
1 0 1100
1 0 1101
1 0 1110
1 0 1111

Verilog code


module bin_as(clk,clr,dir, temp);
input clk,clr,dir;
output reg[3:0] temp;
always@(posedge clk,posedge clr)
begin
if(clr==0)
begin
if(dir==0)
temp=temp+1;
else temp=temp-1;
end
else
temp=4'd0;
end
end module

Simulation result

binary up down counter simulation result

RF and Wireless tutorials

WLAN  802.11ac  802.11ad  wimax  Zigbee  z-wave  GSM  LTE  UMTS  Bluetooth  UWB  IoT  satellite  Antenna  RADAR 


Share this page

Translate this page