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Parallel Load Shift Left Register verilog code

This page covers Parallel Load Shift Left Register verilog code and test bench code of Parallel Load Shift Left Register.

Parallel Load Shift Left Register verilog code

Following is the verilog code of Parallel Load Shift Left Register.

module plsl(pl, sl, slin, Din, clk, reset, Q);
input pl, sl, slin, clk, reset;
input [7:0] Din;
output [7:0] Q;
reg [7:0] Q;

always @ (posedge clk) begin
if (~reset) begin
if (sl) begin
Q <= 'TICK {Q[6:0],slin};
end
else if (pl) begin
Q <= 'TICK Din;
end
end
end

always @ (posedge reset) begin
Q <= 8'b00000000;
end

endmodule

Test code for Parallel Load Shift Left Register

Following is the test bench code of Parallel Load Shift Left Register.

module main;
reg clk, reset, slin, sl, pl;
reg [7:0] Din;
wire [7:0] q;
plsl plsl1(pl, sl, slin, Din, clk, reset, Q);

initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end

initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end

initial begin
sl = 1;
pl = 0;
Din = 8'h42;
#50
sl = 0;
#12
pl = 1;
#5
Din = 8'h21;
#20
pl = 0;
sl = 1;
end

initial begin
forever begin
slin = 0;
#7
slin = 1;
#8
slin = 0;
end
end

endmodule

Verilog source codes

Low Pass FIR Filter
Asynchronous FIFO design with verilog code
D FF without reset
D FF synchronous reset
1 bit 4 bit comparator
All Logic Gates

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