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PRBS Generator verilog code | PRBS Generator Test Bench

This page covers PRBS generator verilog code and mentions test bench script for PRBS generator.

PRBS Generator verilog code

Following is the verilog code of PRBS Generator.

module prbs (rand, clk, reset);
input clk, reset;
output rand;
wire rand;
reg [3:0] temp;
always @ (posedge reset) begin
temp <= 4'hf;
end
always @ (posedge clk) begin
if (~reset) begin
temp <= {temp[0]^temp[1],temp[3],temp[2],temp[1]};
end
end
assign rand = temp[0];
endmodule

PRBS generator test script code

Following is test script code for PRBS Generator.

module main;
reg clk, reset;
wire rand;
prbs pr (rand, clk, reset);
initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
endmodule

Verilog source codes

Low Pass FIR Filter
Asynchronous FIFO design with verilog code
D FF without reset
D FF synchronous reset
1 bit 4 bit comparator
All Logic Gates

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