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4 to 1 Multiplexer Demultiplexer HDL Verilog Code

This page of verilog sourcecode covers HDL code for 4 to 1 Multiplexer and 1 to 4 de-multiplexer using verilog.

4 to 1 Symbol

4 to 1 multiplexer symbol

4 to 1 Multiplexer truth table

Sel1 Sel0 Z
0 0 a
0 1 b
1 0 c
1 1 d

4 to 1 Multiplexer Verilog code


module mux4_1(I0,I1,I2,I3,s2,s1,y,en)
input I0,I1,I2,I3,s2,s1,en;
output y;
assigny<=((~s2)&(~s1)&en&I0)| ((~s2)&(s1)&en&I1)|(s2&(~s1)&en&I2)|(s2&s1&en&I3);
end module

Simulation result

4 to 1 multiplexer simulation result

1 to 4 De-multiplexer symbol

1 to 4 demultiplexer

1 to 4 De-multiplexer truth table

a en Sel1 Sel0 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0 1
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 1 0 0 0
0 1 X X 0 0 0 0

1 to 4 De-multiplexer verilog code


module demux (s2,s1,I,en,y0,y1,y2,y3)
input s2,s1,I,en;
output y0,y1,y2,y3;
assign y0=(~s2)&(~s1)& I& en;
assign y1=(~s2)& s1& I& en;
assign y2=s2&(~s1)& I & en;
assign y3=s2& s1 & I & en;
end module

Simulation result

1 to 4 demultiplexer simulation result

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