Home of RF and Wireless Vendors and Resources

One Stop For Your RF and Wireless Need

4 Bit Binary Asynchronous Reset Counter Verilog Code

This page of Verilog source code section covers 4 Bit Binary Asynchronous Reset Counter Verilog Code. The block diagram and truth table of 4 Bit Binary Asynchronous Reset Counter Verilog Code is also mentioned.

Block Diagram of 4 Bit Binary Asynchronous Reset Counter


4 bit Binary Asynchronous Reset Counter Block Diagram

Truth Table of 4 Bit Binary Asynchronous Reset Counter


4 bit Binary Asynchronous Reset Counter Truth Table

4 Bit Binary Asynchronous Reset Counter Verilog Code

module bin_sync( clk, rst, bin_out);
input clk, rst;
output [3:0] bin_out;
reg [3:0] bin_out;
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge( clkdiv))
begin
if (rst=0)
bin_out=4'b0000;
else
bin_out=bin_out+4'b0001;
end
endmodule



USEFUL LINKS to VHDL CODES

Refer following as well as links mentioned on left side panel for useful VHDL codes.
D Flipflop
T Flipflop
Read Write RAM
4X1 MUX
4 bit binary counter
Radix4 Butterfly
16QAM Modulation
2bit Parallel to serial

USEFUL LINKS to Verilog Codes

Following are the links to useful Verilog codes.
Low Pass FIR Filter
Asynchronous FIFO design with verilog code
D FF without reset
D FF synchronous reset
1 bit 4 bit comparator
All Logic Gates

RF and Wireless tutorials

WLAN  802.11ac  802.11ad  wimax  Zigbee  z-wave  GSM  LTE  UMTS  Bluetooth  UWB  IoT  satellite  Antenna  RADAR 


Share this page

Translate this page