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4 Bit BCD Asynchronous Reset Counter Verilog Code

This page of Verilog source code section covers 4 Bit BCD Asynchronous Reset Counter Verilog Code.

4 Bit BCD Asynchronous Reset Counter Verilog Code

module bin_sync( clk, rst, bin_out);
input clk, rst;
output [3:0] bin_out;
reg [3:0] bin_out;
reg [22:0] div;
reg clkdiv;
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge clkdiv)
begin
if (rst=0)
bcd_out=4'd0;
else if(count<4'd9)
bcd_out=bcd_out+4'd1;
end
endmodule


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Refer following as well as links mentioned on left side panel for useful VHDL codes.
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