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32 bit ALU HDL Verilog Code

This page of verilog sourcecode covers HDL code for 32 bit ALU using verilog. This ALU takes care of arithmetic and logical operations.


D flipflop with synchronous reset

Truth table

Operation Opcode A B Zout
A+B 000 1111 0000 00001111
A-B 001 1110 0010 00001100
A or B 010 1111 1000 00001111
A and B 011 1001 1000 00001000
Not A 100 1111 0000 11110000
A1*B1 101 1111 1111 11100001
A nand B 110 1111 0010 11111101
A xor B 111 0000 0100 00000100

Verilog code

module ALU ( a, b, s, en, y );
input signal [3:0]a, b;
input [3:0]s;
input en;
output signal [7:0]y;
reg y;
always@( a, b, s, en, y );
4�d0: y=a+b;
4�d1: y=a-b;
4�d2: y=a*b;
4�d3: y={4� bww, ~a};
4�d4: y={4� d0, (a & b)};
4�d5: y={4� d0, (a | b)};
4�d6: y={4� d0, (a ^ b)};
4�d7: y={4� d0, ~(a & b)};
4�d8: y={4� d0, ~(a | b)};
4�d9: y={4� d0, ~(a ^ b)};
default: begin end
end case
end module

Simulation result

D flipflop with synchronous reset simulation

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