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2 to 4 decoder HDL Verilog Code

This page of verilog sourcecode covers HDL code for 2 to 4 decoder using verilog programming language.

Symbol

The fig-1 depicts 2 to 4 decoder schematic symbol and following is the truth table for the same.

2 to 4 decoder schematic

Truth Table

E Sel1 Sel0 Y3 Y2 Y1 Y0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 X X 0 0 0 0

Verilog code

module dec2_4 (a,b,en,y0,y1,y2,y3)
input a, b, en;
output y0,y1,y2,y3;
assign y0= (~a) & (~b) & en;
assign y1= (~a) & b & en;
assign y2= a & (~ b) & en;
assign y3= a & b & en;
end module

Simulation result

2 to 4 decoder simulation result

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