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1 bit comparator, 4 bit comparator HDL Verilog Code

This page of verilog sourcecode covers HDL code for 1 bit comparator and 4 bit comparator using verilog.

1 bit comparator Symbol

Following is the symbol and truth table of 1 bit comparator.

D flipflop with synchronous reset

1 bit comparator truth table

a b L E G
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

1 bit comparator Verilog code


module b_comp1 (a, b, L, E,G);
input a, b; output L, E, G;
wire s1, s2;
not X1(s1, a);
not X2 (s2, b);
and X3 (L,s1, b);
and X4 (G,s2, a);
xnor X5 (E, a, b);
end module

Simulation result

D flipflop with synchronous reset simulation



4 bit comparator Symbol

Following is the symbol and truth table of 4 bit comparator.

D flipflop with synchronous reset

4 bit comparator Verilog code


module comp(a,b,aeqb,agtb,altb);
input [3:0] a,b;
output aeqb,agtb,altb;
reg aeqb,agtb,altb;

always @(a or b)
begin
aeqb=0; agtb=0; altb=0;
if(a==b)
aeqb=1;
else if (a>b)

agtb=1;
else
altb=1;
end
end module

Simulation result

D flipflop with synchronous reset simulation

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