ARM exception and interrupt controller
This ARM tutorial covers ARM exception and interrupt controller. Refer following pages for other ARM tutorial contents.
ARM VECTOR TABLE
|Fast Interrupt Request||FIQ||0x0000001c||0xffff001c|
Happens when the processor powers up. Initializes the system, sets up stacks for different processor modes. Highest priority exception Upon entry into the reset handler the CPSR is in SVC mode and both IRQ and FIQ bits are set to 1, mask-ing any interrupts
2nd highest priority. Happens when we try to read/write into an invalid address or access with the wrong access permission. Upon entry into the Data Abort Handler Up on entry into a Data Abort handler IRQ's will be disabled (I-bit set 1), and FIQ will be enabled IRQs are masked, but FIQs are kept unmasked.
Highest priority interrupt IRQ & FIQs are disabled till FIQ is handled.
2nd Highest priority interrupt IRQ handler is entered only is there is no FIQ & Data Abort on-going.
Similar to data abort, but happens on address fetch failure. On entry to the handler, IRQs are disabled, but FIQs remain enabled and can happen during a Pre-Fetch abort.
A Software Interrupt (SWI) exception occurs when the SWI instruction is executed and none of the other higher-priority exceptions have been flagged.
Undefined Instruction exception occurs when an instruction not in the ARM or Thumb instruction set reaches the execute stage of the pipeline and none of the other exceptions have been flagged Same priority as SWI as one can happen at a time. Meaning as the instruction being executed cannot both be an SWI instruction and an undefined instruction at the same time.
ARM Exception handling
Following events happen when an exception happens:
• Store the CPSR to the SPSR of the exception mode.
• PC is stored in the LR of the exception mode.
• Link register is set to a specific address based on the current instruction.. For e.g. for ISR, LR = last executed instruction + 8
• Update the CPSR about the exception
• Set the PC to the address of the exception handler.