Convolution Encoder Implementation
This page describes convolution encoder with example and mention pseudo code of convolutional encoding. It describes useful terms code rate,constraint length,generator polynomials related to convolution encoder.
Let us uderstand Convolution Encoder with following example specifications.
Convolution Encoder (3, 1, 4) specifications
Coding rate: 1/3
Constraint length: 5
Output bit length: 3
Message bit length: 1
Maximal memory order / no. of memory elements = 4
Generator Polynomials: 25 (8), 33 (8), 37 (8)
The purpose of forward error correction is to improve the capacity of a channel by adding some carefully designed redundant information to the data being transmitted through the channel. The process of adding this redundant information is known as channel coding. Convolutional codes operate on serial data, one or a few bits at a time.
Convolutional encoding with Viterbi decoding is a FEC technique that is particularly suited to a channel in which mainly Additive White Gaussian Noise (AWGN) corrupts the transmitted signal.
Convolutional codes are usually described using two parameters:
The code rate = k/n, is expressed as a ratio of the number of bits into the convolutional encoder (k) to the number of channel symbols output by the convolutional encoder (n) in a given encoder cycle.
The constraint length parameter, K, denotes the "length" of the convolutional encoder, i.e. how many k-bit stages are available to feed the combinatorial logic that produces the output symbols.
Closely related to K is the parameter m, which indicates how many encoder cycles an input bit is retained and used for encoding after it first appears at the input to the convolutional encoder. The m parameter can be thought of as the memory length of the encoder. We focus on rate 1/3 convolutional code.
Viterbi decoding has the advantage that it has a fixed decoding time. It is well suited to hardware decoder implementation. But its computational requirements grow exponentially as a function of the constraint length, so it is usually limited in practice to constraint lengths of K = 9 or less.
Input raw binary data is encoded by the binary convolutional encoder, which shall have native rate of 1/3, a constraint length equal to 5, and shall use the following generator polynomials codes to derive its three code bits (X1, X2 and X3):
25 (8), 33 (8), 37 (8)
The generator is depicted in the following figure
Convolutionally encoding the data is accomplished using a shift register and associated combinatorial logic that performs modulo-two addition. (A shift register is merely a chain of flip-flops wherein the output of the nth flip-flop is tied to the input of the (n+1)th flip-flop. Every time the active edge of the clock occurs, the input to the flip-flop is clocked through to the output, and thus the data are shifted over one stage.)
The octal numbers (25) 8, (33) 8, (37)8 represent the code generator polynomials, which when read in binary (10101)2 , (11011)2 and (11111)2 correspond to the Shift register connections to the upper and lower modulo-two adders, respectively as shown in the figure above. Following steps are followed while designing convolutional encoder.
1) Initialize the Memory Registers with zeros on reset
m1=0, m2=0, m3=0, m4=0
2) Store the incoming bit in memory register m_in.
m_in = data_in
3) After the input bit has arrived and data in is valid the operation starts and the output is calculated as
x1 = m_in + m2 + m4;
x2 = m_in + m1 + m3 + m4;
x3 = m_in + m1 +m2 +m3+m4 ;
4) Perform shifting operation
5) Steps 2, 3 and 4 are repeated for the length of input data bits
MATLAB Source code
VHDL Source code
For K=7, rate=1/2,G1=171(octal), G2 = 133(octal), Check VHDL code at following page:
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