PLL | Phase Locked Loop Basics | PLL Operation working
This article mentions PLL i.e. Phase Locked Loop basics and mentions operation or working of PLL or Phase Locked Loop. Link to design of Phase Locked Loop based RF Synthesizer and PLL applications are mentioned.
About PLL: The term PLL is the short form of Phase Locked Loop. The simple PLL circuit consists of Phase Detector, Loop filter, VCO and frequency divider. The PLL circuit is part of RF frequency synthesizer or Local Oscillator found in RF Transceiver i.e. RF frequency converters. Let us understand operation of Phase Locked Loop (i.e. PLL).
PLL | Phase Locked Loop Working Operation
The figure-1 depicts Block Diagram of PLL (Phase Locked Loop) Circuit.
PLL mathematical equation can be expressed as Fo = Fr * N , Hence
Fo can be changed to different values within the range in either of the following ways.
1. keeping Fr fixed and varying N 2. Keeping N fixed and varying Fr.
Following components are used in PLL construction.
Phase Detector (PD) : It compares reference frequency input with frequency divider output. Based on phase comparison PD produces error voltage which is given as input to the loop filter. In simple logic, PD performs almost similar to EX-OR gate.
Loop Filter : There are various configuration employed as loop filter. It is simple low pass filter. It converts error waveform output of the PD into DC voltage for tuning the VCO.
VCO : It is the short form of Voltage Controlled Oscillator. It changes frequency output according to the DC error voltage. Hence adjucts the frequency in case of drift due to temperature variation or ageing. Due to this frequency output of PLL (Phase Locked Loop) remains stable.
Frequency Divider (Divide by N) : It divides frequency output of PLL by integer value of N so that value of this divided frequency will be equal to or near the input reference frequency used in the design.
Refer RF synthesizer design using PLL.
The idea of the above feedback and loop based design is to lock the frequency output of PLL (Phase Locked Loop) with the reference frequency input and also avoid any further drift due to ageing and temperature variation.
Phase Locked Loop operates in any of the 3 stages:
• Free running state: Initially when there is no reference frequency signal is applied, PLL is said to be in free running state.
• Capture state: When the reference signal frequency is applied, VCO frequency starts to change and in some time known as frequency settling time, PLL comes to locked state. The state between free running and locked state is known as capture state. This is the duration during which convergence will happen. • Phase Locked Loop state: This is the state when loop is stable and error voltage from Phase Detector output is zero i.e. output frequency of divider is equal to reference frequency.
Applications of PLL Phase Locked Loop
• Vector Signal Generators and Vector Signal Analyzers
• Function generator
• Scalar Network Analyzer and Vector Network Analyzer
• RF Transceiver (RF Transmitter and RF Receiver)
• RF Local Oscillator and RF Synthesizer