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Full Adder HDL Verilog Code

This page of verilog sourcecode covers HDL code for full adder using verilog.

Symbol

D flipflop with synchronous reset

Truth Table

Input-a Input-b Input-cin Output-SUM Output-Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Full Adder Verilog code


module fulladder ( a, b, c,s,cout)
input a, b,c;
output s, cout;
assign s= a ^ b^c;
assign cout= a & b & c;
end module

Simulation result

D flipflop with synchronous reset simulation

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